1. Field of the Invention
Generally, the present disclosure relates to the manufacture of FET semiconductor devices, and, more specifically, to various methods of forming epi semiconductor cladding materials in the channel region of a FinFET semiconductor device by performing various channel-cladding-last formation techniques, and the resulting semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of so-called metal oxide field effect transistors (MOSFETs or FETs). A transistor includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region that is separated therefrom by a gate insulation layer. Current flow between the source and drain regions of the FET device is controlled by setting the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
Transistors come in a variety of configurations. A conventional FET is a planar device, wherein the transistor is formed in and above an active region having a substantially planar upper surface. In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. FIG. 1B is a cross-sectional view of the device 10 taken through the gate electrode 18 in the gate width (GW) direction of the device 10. As shown in FIG. 1A, in this example, the FinFET device 10 includes a plurality of trenches 14 formed in the substrate 12 that define three illustrative fins 16, a gate structure 18, sidewall spacers 20 and a gate cap layer 22. The fins 16 have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L of the fins 16 corresponds to the direction of current travel in the device 10 when it is operational. The portions of the fins 16 covered by the gate structure 18 are the channel regions of the FinFET device 10. With reference to FIG. 1B, the gate structure 18 is typically comprised of a layer of gate insulating material 18A, e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode 18B for the device 10. In the device 10, the cladding material 17 is the primary current carrying portion of the channel region when the device 10 is operational, i.e., the gate length (GL) direction of the device. Typically, with respect to current day technology, the cladding material 17 may have a thickness 17T of about 2-3 nm. The cladding material 17 is typically an epi semiconductor material, such as silicon germanium, that is formed on the fin 16 by performing known epi deposition processes.
FIGS. 2A-2G depict an illustrative prior art process flow for a FinFET device with a cladded channel region. In FIGS. 2A-2G, the upper drawing is a cross-sectional view taken through the gate structure in the gate width direction (GW) of the device 10. The bottom drawing in FIGS. 2A-2G is a cross-sectional view taken through the middle of one of the fins 16 along the axial length of the fin 16, i.e., in a direction that is parallel to the gate length (GL) direction of the device 10.
FIG. 2A depicts the device 10 after several process operations were performed. First, a plurality of trenches 14 were formed in the substrate 12 to define the initial fins 16 (only two fins are shown in FIG. 2A). After the trenches 14 were formed, a layer of insulating material 21, such as silicon dioxide, was formed so as to overfill the trenches 14. Thereafter, a chemical mechanical polishing (CMP) process was performed to planarize the upper surface of the insulating material 21 with the top of the fins 16 (or the top of a patterned hard mask—not shown). Thereafter, a recess etching process was performed to recess the layer of insulating material 21 between adjacent fins 16 so as to thereby expose the upper portion of the fins 16.
FIG. 2B depicts the device 10 after an epitaxial deposition process was performed to form a cladding material 18 on the exposed portion of the fins 16. The cladding material 18 may be comprised of a variety of different materials, e.g., Si(1-x)Ge(x), and it may be formed to any desired thickness.
FIG. 2C depicts the device 10 after several process operations were performed. First, an illustrative and schematically depicted sacrificial gate structure 20 and gate cap layer 22 (e.g., silicon nitride) were formed above the channel region of the device 10. Illustrative sidewall spacers 24 (e.g., silicon nitride) were formed adjacent the sacrificial gate structure 20. In one illustrative embodiment, the schematically depicted sacrificial gate structure 20 includes an illustrative gate insulation layer (not separately shown) and an illustrative gate electrode (not separately shown).
FIG. 2D depicts the device 10 in one illustrative process flow wherein trenches 23 were formed to remove portions of the fins 16 positioned in the source/drain regions of the device 10. Thereafter, an epi semiconductor material 25 was formed in the source/drain regions of the device 10 by performing a traditional epi growth process, i.e., raised source/drain regions were formed for the device 10. Various ion implant regions would have been formed in the fins 16/substrate 12 at this point in the process flow, e.g., halo implants, extension implants, well implants, etc. Thereafter, one or more heat treatment processes would have been performed to repair any damage to the crystalline structure of the fins 16 due to the various ion implantation processes and to activate the implanted dopant materials.
FIG. 2E depicts the device 10 after a layer of insulating material 26 was formed on the device 10 and after a CMP process was performed to planarize the upper surface of the layer of insulating material 26 with the upper surface of the gate cap layer 22.
FIG. 2F depicts the device 10 after several process operations were performed. First, one or more planarization processes, e.g., CMP processes, were performed to remove the gate cap layer 22 and a portion of the spacers 24 using the sacrificial gate structure 20 as a polish-stop layer. Thereafter, one or more etching processes were performed to remove the sacrificial gate structure 20 relative to the surrounding structures and thereby define a replacement gate cavity 28 where a replacement gate structure will eventually be formed for the device 10. Unfortunately, the cladding material 18 within the channel region of the device 10 is subjected to many of these process operations since it was formed prior to the formation of the sacrificial gate structure 20. As a result, the cladding material 18 within the channel region of the device 10 may be damaged or degraded. More specifically, the cladding material 18 within the channel region may have a variety of divots or defects 19 that may result in the removal of all or a portion of the thickness of the cladding material 18, as depicted in the dashed-line region 30. The amount and extent of damage to the cladding material 18 in the channel region of the device 10 may vary depending upon the device under construction and the exact process flow.
FIG. 2G depicts the prior art device 10 after an illustrative and schematically depicted replacement gate structure 32 and gate cap layer 34 were formed in the replacement gate cavity 28 of the device 10 using well-known techniques. In one illustrative embodiment, the schematically depicted replacement gate structure 32 includes an illustrative gate insulation layer (not separately shown) and an illustrative gate electrode (not separately shown). The gate insulation layer may be comprised of a variety of different materials, such as, for example, a so-called high-k (k value greater than 10) insulation material (where k is the relative dielectric constant), etc. Similarly, the gate electrode of the replacement gate structure 32 may be comprised of one or more metal layers that act as the gate electrode. Unfortunately, the damage to the cladding material 18 in the channel region of the device can adversely affect device performance.
The present disclosure is directed to various methods of forming one or more cladding materials in the channel region of a semiconductor device by performing various channel-cladding-last formation techniques, and the resulting semiconductor devices that may reduce or eliminate one or more of the problems identified above.